Sources of Variation: The
primary sources of variation that necessitate derates are:
·
PVT (Process, Voltage, Temperature)
Variations: These are inter-chip variations.
o Process:
Variations in manufacturing (e.g., lithography wavelength, defects) can alter
transistor parameters like oxide thickness, dopant levels, and physical
dimensions (W/L), which in turn affect threshold voltage (Vt) and current (I),
and thus cell delay. Dies at the center of a wafer are more accurate than those
at the periphery.
o Voltage:
Supply voltage fluctuations (due to IR drop, supply noise, battery charge
levels) directly impact current and cell delay. Lower technology nodes with
lower supply voltages see a higher percentage of variation.
o Temperature:
Ambient temperature and on-chip hot spots (due to high switching activity)
affect cell delays. For deep sub-micron technologies, temperature inversion
(where delay decreases with increasing temperature at lower voltages) can
occur.
·
RC Variations: Interconnect delay is
increasingly dominant. Variations in CMP, photolithography, and etch processes
affect wire dimensions, leading to RC variations.
·
OCV (On-Chip Variation) / Local Variations:
These are intra-chip variations, meaning identical cells at different locations
on the same chip and in the same corner can exhibit different delays.
Factors include IR drop, metallization mismatches, CMP effects, Vth/mobility
mismatches, local temperature variations, and toggling activity mismatches
(aging). OCV is categorized into:
o Random
Variations: Non-deterministic, no spatial correlation, hard to predict
(e.g., gate oxide thickness, implant doses). Their effect tends to cancel out
over longer path depths.
o Systematic
Variations: Deterministic, can be modelled, exhibit spatial correlation
(e.g., gate length/width, interconnect width due to proximity/density effects).
Proportional to cell location.
·
Simple OCV Derates (Global Derates):
Applying a single, fixed derate percentage (e.g., +/-6%) to all cells/nets for
late/early paths using set_timing_derate.
o Problem:
Overly pessimistic because it applies the worst-case variation (derived from
the most sensitive cell) to all cells, leading to over-optimization, increased
power consumption, and longer STA cycles.
·
AOCV (Advanced OCV): Reduces pessimism by
applying derates based on cell type, path depth (random variations tend to
cancel), and distance (systematic variations increase with distance). AOCV is
more accurate than OCV, especially for nodes like 65nm and below.
o Flaws:
AOCV often uses the worst-case timing arc for a cell's derate and doesn't
account for variations due to input slew, output load, or operating conditions
of side inputs, potentially being too optimistic or pessimistic.
·
POCV (Parametric OCV): A more realistic,
statistical approach that overcomes AOCV limitations by making OCV derate
factors dependent on input slew and output load.
o It
assumes cell delay follows a normal distribution (Gaussian curve) around a
nominal delay (mean, μ) with a standard deviation (σ). Typically, analysis is
done at 3σ (covering ~99.7% of variations).
o Random
variations are modeled using this statistical approach (μ, σ) instead of
min-max values, reducing pessimism as extreme delay values are less probable.
o Systematic variations are still handled using distance-based derates, similar to AOCV.
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