o
CTS tools on global skew to start implementing
clock tree. The idea is that minimizing the global skew will automatically
minimize the local skew as global skew is the upper bound of local skew.
o
Global skew balancing attempts to make the
propagated clock timing match the ideal mode clock timing by balancing the
insertion delay (clock latency) between all sinks.
o If you are working on a block and it is a full chip clock domain, the global skew will make effect at full chip timing for global clock balance. You need to meet the latency &. skew requirements for chip timing close.
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