o Signal
Integrity (SI): Quality of an electrical signal as it travels from a driver
to a receiver through an interconnect. Major SI concerns include:
o Crosstalk:
Unwanted coupling between adjacent signal nets.
o IR
Drop: Voltage drop on the power/ground network affecting cell performance.
o Electromigration
(EM): Reliability issue due to metal migration under high current density.
o Timing
Jitter/Phase Noise: Variations in the timing of signal edges, especially
critical for clocks.
o Crosstalk
Noise/Glitch: It occurs when a switching signal on one net (the aggressor)
induces a voltage disturbance (a noise bump or "glitch") on a nearby
net (the victim) that is supposed to be holding a constant logic level
(static).
o Mechanism:
The coupling capacitance (Cc) between the aggressor and victim nets allows the
rapid voltage change (dV/dt) on the aggressor to inject current onto the victim
net, causing its voltage to temporarily deviate from its steady VDD or VSS
level.
o Impact:
If the induced voltage glitch is large enough (exceeds the noise margin of the
receiving gate on the victim net) and lasts long enough, it can cause the
receiving gate to momentarily interpret the wrong logic level, leading to
functional failure. Even smaller glitches can increase cell power consumption
or slightly affect timing.
o https://teamvlsi.com/2020/06/crosstalk-noise-and-crosstalk-delay-effects-of-crosstalk.html
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