How to ensure clock tree quality?

o   Meeting Skew Targets: Verify achieved skew (global and local/group) against specified targets using CTS reports (report_clock_timing).

o   Meeting Latency Targets: Check min/max insertion delays against requirements.

o   Meeting DRCs: Ensure no max_transition, max_capacitance, or max_fanout violations

o   Duty Cycle Preservation: Check for duty cycle distortion. Ensure minimum pulse width requirements are met.

o   Balanced Structure: Visually inspect the tree or use tool reports to check for reasonably balanced branches. Global skew gives idea on how overall CTS is balanced.

o   Use appropriate clock buffers (balanced, low variation).

o   Apply NDRs (Non-Default Rules like shielding, double spacing) during clock routing to minimize crosstalk susceptibility.

o   Power Efficiency: Check the number and size of inserted clock buffers/inverters. Ensure the tool performed power optimization if enabled.

o   Routability: Analyze post-CTS congestion maps.