o Analyze Connectivity (Flylines) – all fanin, all_fanout.
o
Use trace macro feature of Innovus.
o Group
by Hierarchy/Connectivity
o Consider
Data Flow:
o Periphery
Placement: Generally place macros around the edges of the core area,
leaving the central area for standard cells. This simplifies power delivery to
macros and avoids blocking standard cell placement/routing in the core center.
o Pin
Accessibility: Orient macros so their pins face towards the core logic they
connect to, minimizing wire length and routing complexity.
o Channel
Spacing: Leave adequate space (channels) between macros and between macros
and the core boundary. This space is needed for:
o Routing
nets connecting to macro pins.
o Placing
buffers/inverters near macro pins for timing optimization.
o Power
strap routing.
o The
required channel width depends on pin density, number of connections, and
available routing layers. A rough estimate: Channel Width ≈ (Number of Pins *
Pin Pitch) / (Number of Available Routing Layers). Add margin (5-10%).
o Avoid
Notches
o Alignment:
Align macros neatly to facilitate power grid construction and routing.
o Keep-out
Margins (Halos): Define halos around macros (especially hard macros) to
prevent standard cells from being placed too close to macro pins, which can
cause congestion. The size depends on pin density and expected buffering needs.
o Power Considerations: Place power-hungry macros close to power pads/bumps if possible. Ensure adequate power strap access between macros.
Noise Sensitivity: Separate noise-sensitive analog macros from noisy digital macros.
0 comments:
Post a Comment