How to resolve LEC mismatches? What is non-equivalent point?

o   LEC (Logical Equivalence Check): Compares Golden netlist or RTL with netlist at any given point in PnR flow to check functionality is same or not.

o   Tools like Synopsys Formality or Cadence Conformal are used.

o   Non-Equivalent Point: A point (typically a primary output port or a sequential element input/output) in the two designs being compared where the LEC tool has determined that the logic functions driving that point are not equivalent. This indicates a functional difference between the "golden" reference design and the revised/implemented design, meaning the optimization or synthesis process has introduced a functional bug.

o   Equivalence Checking Overview: https://www.synopsys.com/glossary/what-is-equivalence-checking.html

o   LEC Steps: https://semiconductorclub.com/logic-equivalence-check/