What are the goals of CTS?

o   Minimize Clock Skew

o   Meet Insertion Delay Targets

o   Achieve Target Transition Times (Slew): Ensure the clock signal edges are sharp (fast transitions) throughout the network to guarantee reliable clocking of sequential elements and minimize sensitivity to noise. Meet max_transition DRC constraints.

1.       Too tight trans causes more bufs/inv and increases area, power and latency.

2.       Loose trans can cause more leakage, sensitive to noise and increased delay.

o   Meet Other DRCs: like max_capacitance and max_fanout

o   Minimize Power Consumption: Build the clock tree with optimum power possible.

o   Maintain Signal Integrity and Routability:

o   No timing violations.