o
Placement Database: The design database
after placement is complete, containing the locations of all standard cells
(including clock sinks like flip-flops and clock gates) and macros. – it covers
Timing lib. Tech lef, std cell lef, SDC etc.
o CTS
Specification File .ctstch, .cts_spec, This file (or
equivalent tool settings) provides detailed instructions for building the clock
tree:
- Target Skew:
Maximum acceptable skew between sinks in the same clock domain or skew
group.
- Target Max/Min Latency:
Desired range for insertion delay.
- Target Max Transition:
Maximum allowed transition time for clock nets.
- Buffer/Inverter List:
Specifies the list of buffers and inverters the tool is allowed to use for
building the tree (often restricts to specific drive strengths or balanced
cells).
- DRC Constraints:
Max capacitance, max fanout limits specifically for clock nets.
- NDR (Non-Default
Rules): Specifies special routing rules (e.g., double width, double
spacing, shielding) to be used for clock nets to improve signal integrity
and reliability.
- Routing Layers:
Preferred top and bottom metal layers for clock routing.
- Clock Tree Exceptions:
Defines pins to be treated specially:
- Stop/Sink Pins (Default):
Normal clock endpoints to be balanced.
- Exclude Pins: Excluded
from skew/latency balancing but still receive the clock and DRV fixing
(e.g., output ports, Multiplexer select pin )
- Ignore Pins: Completely
ignored by CTS balancing and DRC fixing (e.g., non-clock pins driven by
clocks, test pins).
- Float Pins: Similar to
Exclude pins but allow specifying a pin delay range for balancing (used
for macro models).
- Non-stop pins: trace
through the endpoints that are normally considered as endpoints of the
clock tree. Ex, The clock pin of sequential cells driving generated clock
are implicit non-stop pins. Clock pin of ICG.
- Skew Groups:
Defines groups of sinks that should be balanced together, potentially with
different skew targets than other groups.
- Clock Tree Structure
Hints: May allow specifying preferred structures (e.g., H-tree for
certain branches) or buffer placement constraints. Multi tap etc.
o CTS
Spec File Contents: https://ivlsi.com/cts-spec-file-vlsi-physical-design/
o CTS
Overview: https://www.scribd.com/document/698125285/CLOCK-TREE-SYNTHESIS
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