What is the difference between the route and route_opt stage?

o   Routing (routeDesign or similar): This stage focuses on physically connecting the pins of all standard cells and macros. goal is connectivity and DRC correctness.

o    Sub-stages: Often involves Global Routing (planning paths through routing regions/GCells), Track Assignment (assigning nets to specific tracks), and Detail Routing (drawing the exact wires and vias, ensuring DRC rules like spacing/width are met).

o    Timing/Optimization: Basic timing considerations might influence routing choices (e.g., prioritizing critical nets), but large-scale timing optimization (like cell sizing, buffer insertion) is not the primary focus. The main goal is to achieve a DRC-clean, fully routed design.

o   Route Optimization (route_opt or optDesign -postRoute or similar): This stage occurs after initial detailed routing. Its primary goal is timing closure and signal integrity improvement on the routed design.

o    Buffer Insertion/Sizing/Swapping.

o    Gate Sizing/Swapping: Resizes/swaps logic gates for timing/power.

o    Incremental Routing: Makes small adjustments to routes to fix timing or SI issues