What is set_case_analysis?

o   set_case_analysis: particular port or pin in the design should be treated as having a constant logic value (0 or 1) for the duration of the timing analysis run (or for specific modes).

o   Purpose:

o   Mode Setting: To model different operating modes of the chip (e.g., functional mode vs. test mode) where certain control signals are tied high or low.

o   Disabling Logic: By setting control signals (like multiplexer selects, enables) to constant values, specific logic paths can be disabled for timing analysis,

o   If a MUX select is set constant, only the path through the selected input is timed.

o   If an AND gate input is set to 0, its output is treated as 0, disabling downstream paths.

o   If an OR gate input is set to 1, its output is treated as 1.

o   Example: Suppose a design has a test mode enable signal TEST_MODE_EN at an input port. In functional mode, this signal is low (0), and in test mode, it's high (1). To analyze timing specifically for functional mode:

set_case_analysis 0 [get_ports TEST_MODE_EN]