o Via Pillar: A structure used in advanced process nodes (like FinFET nodes) to create a lower-resistance vertical connection between metal layers compared to traditional single vias or via arrays. It typically consists of:
o Stacked,
short metal segments ("fingers") on intermediate metal layers,
aligned vertically.
o These
segments are connected by vias above and below, essentially forming a
"pillar" of alternating via and short metal bar segments running
vertically through multiple layers.
o Why
Use It?
o Usually
used in Power planning and secondary PG routing. Can be used in clock and
signal or on critical cells pin connections.
o Generally,
this feature is used in restricted ways and the via pillar is usually attached
to the library pin—everywhere that cell is used it will have a via pillar,
typically on the output
o Reduce
Via Resistance: A via pillar provides multiple parallel paths for current
between the top and bottom connection points, significantly reducing the
overall effective vertical Resistance.
o Improve
Electromigration (EM) Robustness: By distributing the current across
multiple paths within the pillar structure, the current density in any single
via or metal segment is reduced, improving reliability against electromigration
failures.
o Issues
that cause poor insertion of via pillar:
o
Track alignment issue/ PG stripe
overlapping/Insufficient Margin Area
o
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/tsmc-n7
o Via
Pillar Overview: https://eternallearning.github.io/via-pillar/
o
http://archive.sigda.org/ispd/slides/2020/ispd20_via_pillar_placement.pdf
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