o Header Switches: Use PMOS transistors placed between the main VDD grid (always-on supply) and the switchable VDD rail of the power domain (VDD_SW). The PMOS gate is controlled by the sleep/enable signal. When OFF (sleep signal asserted), they disconnect the domain from VDD.
o
Footer Switches: Use NMOS
transistors placed between the switchable VSS rail (VSS_SW) of the power domain
and the main VSS grid (always-on ground). The NMOS gate is controlled by the
sleep/enable signal. When OFF, they disconnect the domain from VSS.
o
Combined Header/Footer: Some designs
might use both header and footer switches for more robust power cut-off,
although this adds complexity and area.
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