Why timing correlation issues occur between block level and top level, even with the same clock source?

o   update_io_latency not done at block level. This ensures proper clock tree built for IO paths and gives feedback to top level tree so tree is balanced for io paths.

o   IO constraints like input_delay and output_delay is assumption. Actual delay might be different and hence misscorelation.

o   Different derate factors at top level or OCV variation?

o   May introduce additional SI effect during top level