Can an AND gate replace an ICG if glitch is handled

o   If used AND gate as gater, we need to make sure that, EN only switched when clock is low. Otherwise, it can create glitches. Let’s say this is taken care somehow.

o   But still enable can only switch after x time of clock falling edge and it should stay stable before y time of clock rising edge. If this is not taken care, it can still create issues. This is exactly setup and hold time checks of ICG cells.

o   ICG cells are specifically characterized in the library for clock gating checks (setup/hold on the enable relative to the clock). Standard AND/OR gates are not. Using a standard gate for clock gating bypasses these critical checks in STA tools.

o   PnR and CTS tools recognize ICG cells as clock gating elements and handle them correctly during clock tree building (e.g., balancing up to the clock input pin, recognizing the enable pin). They may not correctly interpret a standard AND/OR gate used for gating.

o   So, Even if glitches are taken care and EN signal is perfectly timed to avoide glitches, it bypasses standard clg checks so should not be used.