Where should clock gaters be placed (near sink or source)?

o   If you place ICG near to source, dynamic power consumption will reduce. This is because most of the clock buffers are in fanout of clock gater. These clock buffers will not toggle when clock gating is enabled.

o   But placing ICG near to source increases the uncommon paths. These uncommon paths can behave differently, so during STA these need to be taken into account that extra uncertainty.

o   If you place ICG near to sink, most of the clock buffers are in common path. It is easy to met timing compared to scenario-1.

o   But at the same time dynamic power consumption is increased.

o   Remember, there is trade-off between power and timing.

o   Ideally, Integrated Clock Gating (ICG) cells should be placed physically close to the group of flip-flops (sinks) they are gating.

o   Improve CTS Balancing: CTS tools balance delay up to the inputs of the ICG cells. Placing the ICG close to the sinks means the final, unbuffered gated clock segment is short and contributes less variable delay, making overall skew balancing more predictable.

o   Reduce Enable Net Impact: While the enable signal net might become longer if the enable logic originates far away, Placing the ICG far from sinks would create a very large, high-capacitance net driven by the ICG output, which is undesirable.