Can we see negative setup and hold values in the library? Why? What is the impact?

Yes, it is possible and quite common to see negative setup and hold times specified in standard cell timing libraries (.lib).

o    There are internal delays along the clock path and data path within the cell, from the input pins to the internal latch.

§  Negative Setup: If the internal clock path delay is significantly longer than the internal data path delay plus the internal latch's intrinsic setup time, the data pin (D) can actually change after the active clock edge at the clock pin (CK) and still be captured correctly.

§  Think of it as internal extra added skew that is helping setup violation.

§  Negative Hold: If the internal data path delay is significantly longer than the internal clock path delay minus the internal latch's intrinsic hold time, the data pin (D) can change before the clock edge at the pin (CK) has fully propagated to the internal latch, and the previous data value will still be correctly held.

§  Consistency Check: While individual setup or hold can be negative, their sum (Tsetup​+Thold​) for a given pin/clock edge combination must generally be positive to represent a physically realizable sampling window. Libraries are usually checked for this consistency.

o    https://www.youtube.com/watch?v=Wys-Q2xVzaE

o    Library Definitions: https://www.physicaldesign4u.com/2020/05/how-setup-and-hold-checks-are-defined.html