Difference between Static and Dynamic power. How can dynamic power be fixed/reduced?

o   Static Power: Power consumed when the circuit is powered ON but not actively switching. It's primarily due to leakage currents flowing through transistors that are supposed to be OFF.

o    Main Components: Subthreshold leakage, gate leakage, junction leakage.

o    Factors: Increases significantly with lower threshold voltages (Vt) and at smaller technology nodes. Also increases with temperature.

o   Dynamic Power: Power consumed during the switching of logic states (when signals transition between '0' and '1').

o    Main Components:

§  Switching Power: Power needed to charge/discharge the load capacitance of gates and interconnects (Psw​=αCVdd2​f). This is usually the dominant component.

§  Internal (Short-Circuit) Power: Power consumed due to the brief direct path between VDD and VSS when both PMOS and NMOS transistors are momentarily ON during input transitions.

o   Fixing/Reducing Dynamic Power:

o    Reduce Voltage (Vdd​): Most effective method due to the quadratic relationship (Vdd2​). Techniques include dynamic voltage scaling (DVS) or using multiple voltage domains.

o    Reduce Frequency (f): Lowering the clock frequency directly reduces dynamic power. Dynamic frequency scaling (DFS) can be used.

o    Reduce Switching Activity (α):

§  Clock Gating:

§  Architectural/RTL Optimization: Minimize unnecessary computations, choose efficient logic structures.

o    Reduce Capacitance (C):

§  Cell Sizing: Use smaller cells (lower drive strength) where timing permits, as they have lower input capacitance.

§  Layout Optimization: Shorter wire lengths reduce interconnect capacitance.