o Decap Cells (Decoupling Capacitors): These are essentially capacitors (often MOSCAPs) placed near switching logic.
o Need:
to supply instantaneous current demands during fast switching events,
stabilizing the power supply voltage (VDD/VSS) and mitigating dynamic IR drop
and voltage noise on the power grid
o Filler
Cells: These cells fill the empty spaces left in standard cell rows after
placement and optimization. They typically only contain VDD/VSS connections and
substrate/well contacts.
o Need:
Ensure N-well and substrate continuity for proper biasing. Provide continuous
power rail connections along the rows. Required for manufacturability (uniform
density for CMP - Chemical Mechanical Polishing).
o Tie
Cells (Tie-High/Tie-Low): These cells provide a clean connection to VDD
(Tie-High) or VSS (Tie-Low). They connect the input pins of standard cells that
require a constant logic '1' or '0' directly to the power rails.
o Need:
Avoids connecting sensitive gate inputs directly to the main power rails, which
can cause issues like antenna violations or noise injection. Provides a
reliable, characterized source for logic '1'/'0'.
o Endcap
Cells (Boundary Cells): Placed at the ends of standard cell rows or
boundaries of blocks.
o Need:
Properly terminate the N-wells and substrate at row ends, ensuring correct
potential and preventing DRC violations. Can sometimes include small decap
capacitance. Helps in reducing well proximity effect.
o (Well
Tap Cells): Similar to filler cells but specifically designed to provide
frequent substrate and N-well contacts within the rows to prevent latch-up and
ensure proper body bias. Often combined with filler functionality.
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