How do you decide which scenarios/corners to use for PnR vs. Signoff?

The selection involves a trade-off between PnR runtime/effort and signoff accuracy/coverage.

o   Signoff: Aims for comprehensive coverage of all conditions the chip might experience. It typically includes:

o    Multiple PVT Corners: Extremes of Process (SS, FF, SF, FS), Voltage (min, max), and Temperature (min, max), plus typical (TT).

o    Multiple RC Corners: Worst/Best RC combinations (RCworst, RCbest, Cworst, Cbest, potentially crosstalk corners).

o    Multiple Modes: Functional modes, test modes (Scan Shift, Scan Capture, BIST), potentially low-power modes.

o    Combined Scenarios: A large set of scenarios combining PVT, RC, and Modes (e.g., SSG_LVT_low_temp_max_volt_rcworst_func_mode). The exact number can range from tens to hundreds depending on the design complexity and requirements.

o   PnR (Placement & Route): Aims for efficient optimization while providing good correlation to signoff.

o    Fewer PVT Corners: Often limited to worst-case setup (e.g., SSG_low_volt_high_temp) and worst-case hold (e.g., FFG_high_volt_low_temp) corners, plus maybe a typical corner.

o    Fewer RC Corners: Typically restricted to RCworst for setup optimization and RCbest for hold fixing during relevant stages.

o    Goal: The selected PnR scenarios should ideally encompass the conditions that are most likely to limit performance (setup) or cause hold failures. The choice is based on:

§  Past experience and data showing which corners are typically timing-limiting for that technology/design style.

§  Analysis of library behavior across corners.

§  Project requirements (e.g., if a specific test mode is performance-critical).

§  Tool capabilities (Multi-Mode Multi-Corner - MMMC PnR allows handling more scenarios concurrently, but still fewer than signoff).