How do you handle cases of IR drop—both static and dynamic—especially if the standard methods are not applicable?

o   Handling Static IR Drop: Static IR drop is primarily due to the resistance of the power grid (Vdrop​=Iavg​×Rgrid​). If you cannot improve Rgrid​ (by widening straps/adding vias):

o   Reduce Average Current (Iavg​):

o    Downsize Non-Critical Cells: Replace cells contributing significantly to static leakage in the affected region with smaller drive-strength variants (if timing permits).

o    VT Swapping (High VT): Swap cells to higher Vt variants (LVT -> SVT -> HVT) in the affected area. Higher Vt cells have significantly lower leakage current. This requires available timing slack.

o    Power Gating (Architectural): If the block can be periodically shut down using power gating, its contribution to average static IR drop over time is reduced (This is a design architecture change, not a simple fix).

o   Optimize Power Grid Path: Ensure the existing power grid connections are optimal. Sometimes, reconnecting a cell group to a different, less resistive part of the existing grid (if possible without causing other issues) might help slightly.

o   Re-evaluate Floorplan: Move the high-leakage block to an area with a stronger existing power grid, if possible.

o   Handling Dynamic IR Drop (when standard fixes are limited): Dynamic IR drop is due to peak current demands during switching (Vdroop​≈LdtdI​+Ipeak​R). If you cannot add decaps (the primary fix) or strengthen the grid:

o   Reduce Peak Current (Ipeak​ / dI/dt):

o    Activity Spreading (Timing Adjustment): If multiple cells switch simultaneously causing a large current spike, try adjusting timing slightly (e.g., using useful skew, adding small delays) on non-critical paths to stagger the switching times, thus reducing the peak current draw at any single moment. This is complex and has timing implications.

o    Downsize Switching Cells: Reduce the size/drive strength of the heavily switching cells, if timing slack allows. Smaller cells draw less peak current.

o    VT Swapping (High VT): Using higher Vt cells can slightly reduce peak current (due to slower switching), but the main impact is slower performance.

o    Reduce Clock Frequency: Lowering the clock frequency reduces the dI/dt component and overall activity (architectural change).

o    Clock Gating: Ensure clock gating is aggressively applied to prevent unnecessary switching in the affected region.

o    Spreading cells

o   Optimize Local Power Delivery: Ensure the existing connections from the local power rails/straps to the high-switching cells are as low-resistance as possible (e.g., maximizing local vias if that specific fix is allowed).

https://community.cadence.com/cadence_technology_forums/f/digital-implementation/1061/static-and-dynamic-power-ir-analysis