How do you instruct your tools to resolve post-clock violations? What role does “useful skew” play in these scenarios?

o   Enable Post-CTS/Post-Route Optimization:

o   Innovus: optDesign -postCTS (after CTS), optDesign -postRoute (after routing). These commands invoke timing-driven optimization engines.

o   ICC2: clock_opt -stage cts_optimize (after CTS build), route_opt (performs routing and optimization iteratively).

o   Specify Effort Levels: Increase the optimization effort.

o   Innovus: setOptMode -effort high|extreme

o   ICC2: Options within place_opt, clock_opt, route_opt to control effort (e.g., -effort high).

o   SI-Aware Optimization: Ensure Signal Integrity (crosstalk) aware optimization is enabled if SI violations are contributing to timing issues.

o   Innovus: setOptMode -crosstalkAware true

o   ICC2: set_si_options -delta_delay true -glitch true; route_opt -xtalk_driven

 

o   Role of "Useful Skew":

o    Setup Violation Fixing:

§  If a path is failing setup, the tool might intentionally delay the capture clock path or speed up the launch clock path. Increasing the skew to help setup.

o    Hold Violation Fixing:

§  If a path is failing hold, the tool might intentionally delay the launch clock path or speed up the capture clock path effectively increasing hold slack.

o   Innovus: setUsefulSkewMode

o   setOptMode -usefulSkew true

o   Mechanism: The tool achieves useful skew by selectively adding/removing buffers or resizing existing clock buffers on specific branches of the clock tree to achieve the desired delay difference between the launch and capture clock pins of critical paths.

o   https://www.design-reuse.com/articles/57091/timing-optimization-technique-using-useful-skew-in-5nm-technology-node.html