In a low power project with multiple corners (e.g., low_svs, turbo), how do you choose the appropriate timing corner for each step?

o   In a low-power project with specific operating performance points (OPPs) like:

o   "low_svs" (Low Standard Voltage Swing, likely a power-saving mode)

o   "turbo" (a high-performance mode, likely at a higher voltage),

o   Setup Analysis:

o   low_svs Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddL and worst-case temperature (often high temp for CMOS). This is SSG_VddL_HighTemp_RCworst. This represents the slowest the logic will be in low power mode.

o   turbo Mode: Analyze setup at the slowest process corner (SS/SSG) combined with VddH and worst-case temperature. This is SSG_VddH_HighTemp_RCworst. This is the absolute performance bottleneck.

o   Hold Analysis:

o   low_svs Mode: Analyze hold at the fastest process corner (FF/FFG) combined with VddL and best-case temperature (often low temp). This is FFG_VddL_LowTemp_RCbest. Data paths are fastest here.

o   turbo Mode: Analyze hold at the fastest process corner (FFG) combined with VddH and best-case temperature. This is FFG_VddH_LowTemp_RCbest.

o   Power Analysis:

o   Static (Leakage) Power: Worst case leakage is usually at the fastest process corner (FF/FFG) with highest voltage (VddH) and highest temperature, for cells active in that state. Also analyze at typical and low power states.

o   Dynamic Power: Typically analyzed under typical process (TT) and nominal/turbo voltage (VddH) with realistic switching activity for each mode (turbo mode will likely have higher activity).