o Path Summary:
o
Startpoint: Where the path begins (input
port or flop clock pin).
o
Endpoint: Where the path ends (output
port or flop data input pin).
o
Path Group:
o
Path Type: Setup, Hold, Recovery,
Removal, Min Pulse Width, etc.
o
Slack:
o
Data Arrival Time Path: Details the delay
contribution of each element along the data path:
o
Clock Network Delay (Launch): Latency
from clock source to launch flop clock pin (relevant post-CTS).
o
Clock-to-Q Delay: Delay through the
launch flop.
o
Logic Delay: Delay through each
combinational cell (gate) on the path.
o
Net Delay: Delay through the interconnect
wires connecting the cells (RC delay).
o
Incremental Delay & Path Delay:
Cumulative delay at each stage.
o
Fanout – Load – Slew at each point (same
to check in required time path )
o
Cell location – gives idea if cells are
placed far away or not.
o
Data Required Time Path: Details the time
budget available:
o
Clock Period: Target clock cycle time (
phase shift )
o
Clock Network Delay (Capture): Latency
from clock source to capture flop clock pin (relevant post-CTS).
o
Clock Uncertainty: Skew + Jitter margins.
o
Library Setup/Hold Time: The intrinsic
requirement of the capture flop.
o
CPPR/CRPR Adjustment: Pessimism removal
credit applied (relevant in OCV modes post-CTS).
o
Cell/Net Details: Often shows input
transition (slew), output capacitance (load), and specific delay values for
each cell and net instance in the path.
o
Analysis - What to Look For:
o
Magnitude of Slack: How large is the
violation (negative slack) or margin (positive slack)?
o
Dominant Delay Components: Is the delay
dominated by cell delay (logic complexity) or net delay (long wires, high
capacitance)?
o
Number of Logic Levels: How deep is the
combinational logic path? Very deep paths are inherently harder to time.
o
Cell Types: Are slow (HVT) cells used on
a critical setup path? Are very fast (LVT) cells causing hold issues? Are there
unusually slow/fast library cells?
o
Net Characteristics: Are there very long
nets? Nets with high capacitance or slow transition times?
o
Clock Path Skew (Post-CTS): What is the
skew between launch and capture clock paths? Is it helping or hurting the
specific check (setup/hold)?
o
Constraints: Are the constraints applied
to this path correct (clock period, I/O delays, exceptions)? Is it accidentally
a false or multicycle path?
o Pre-Route
vs. Post-Route Analysis Differences:
o
Pre-route – estimated RC, usually optimistic. So
if any Net gives high delay, needs careful consideration
o
Post route, we have actual RC delay, actual
crosstalk impact as well and hence violations may increase.
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