What are sanity checks after route for STA?

o   Netlist vs. Layout: LVS clean. If design has shorts, it results in inaccurate extraction for those nets. So LVS clean is preferred.

o   SPEF File Validity: Check if any issues or critical warning in extraction flow. If there are ignored nets during extraction, paths with those nets will not have accurate timing.

o   Other consistency chek like Lib and SDC, no missing constraints.

o   Annotation Check (report_annotated_delay/check): After reading SPEF/SDF, verify that parasitic delays and checks have been successfully annotated onto the design nets and cells. Look for warnings about unannotated elements.

o   Basic Timing Check: Run a quick report_timing for the top few paths. Unusually massive violations (many times the clock period) or unexpected critical paths might indicate fundamental issues with inputs (wrong SDC, bad SPEF) rather than just needing optimization.