How to fix hold violations?

o   Buffer/Delay Cell Insertion: Insert buffers or dedicated delay cells into the data path segment between the launch and capture flops.

o   Cell Sizing (Downsizing): Replace cells on the data path with slower, smaller drive-strength variants (e.g., X4 -> X1). Smaller cells have higher intrinsic delay.

o   VT Swapping (Higher Vt): Replace cells on the data path with slower, higher-Vt variants (LVT -> SVT -> HVT).

o   Useful Skew (Negative Skew): Intentionally delay the launch clock path or speed up the capture clock path. Reduce the skew if possible.

o   Routing Detours: Reroute the data path net using a longer path zigzag or slower lower metal layers to increase its delay.

o   Add dummy load on the net.

o   Hold fixing is critical because unlike setup violations (which can sometimes be addressed by lowering clock frequency), hold violations are frequency-independent and can cause functional failure at any speed if not fixed.