o Max_cap vio = the total capacitive load driven by an output pin exceeds the limit specified in the library for that pin. This load includes the input pin capacitance of all driven gates and the capacitance of the interconnect wire. Fixing involves reducing the load seen by the driver or increasing its driving capability:
1.
Buffer Insertion: Insert one or more
buffers on the net. Reducing load of longer interconnect.
2.
Driver Cell Sizing (Upsizing): Increase
the drive strength of the cell driving the net. Stronger cells are often
characterized to handle higher capacitive loads (their max_capacitance limit
might be higher).
3.
Fanout Load Cell Sizing (Downsizing): If
possible (i.e., if timing permits on the fanout paths), reduce the size of the
gates being driven (the load cells). Smaller gates have lower input pin
capacitance.
4.
Load Splitting/Cloning: Clone the driving
cell. Each clone drives a subset of the original fanout nets/cells, reducing
the capacitance driven by any single output pin.
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