If setup & hold are clean but there are clock DRVs, can the block be closed? How to identify and fix clock DRVs?

o   NO. Even if setup and hold timing checks pass, significant Design Rule Violations (DRVs) either on data or clock needs to be fixed.

o   Reliability: Slow transitions (max_transition violation) make sequential elements susceptible to noise, glitches, and potential metastability

o   Timing Accuracy: buffers/inverters are characterized based on expected input transitions and output loads. Violating max_transition or max_capacitance means the library timing models used for setup/hold analysis are inaccurate, invalidating the "clean" timing result. The actual delays might be worse.

o   Power: Slow transitions increase short-circuit power consumption in the clock buffers and the receiving flip-flops.

o   Jitter: Poor signal integrity on the clock net can increase clock jitter

o   Identifying Clock DRVs:

o   STA Reports: Run STA reports specifically targeting DRVs on the clock tree.

o   report_constraint -all_violators (or similar) will list max_cap, max_tran violations. Filter for clock nets/pins.

o   Fixing Clock DRVs: These are fixed using techniques similar to fixing DRVs on signal nets, but applied specifically to the clock tree, often during post-route optimization or ECOs:

o   Buffer Insertion: Insert additional clock buffers/inverters to break long nets (fixes max_cap, max_tran) or to isolate high capacitance sinks.

o   Cell Sizing (Upsizing): Increase the drive strength of the clock buffer driving the violating net segment. A stronger driver provides faster transitions and can handle higher capacitance.

o   Cell Sizing (Downsizing): If a buffer is oversized for its load, downsizing it can reduce the load on the previous stage, potentially fixing a violation there.

o   VT Swapping (Lower Vt): Swapping to lower Vt clock buffers can provide faster transitions (fixing max_tran) but increases leakage.

o   Net Topology/Routing Changes: Minor re-routing (e.g., layer change, shortening path) might slightly reduce capacitance or resistance, helping fix violations (less common as a primary fix).

o   Load Splitting/Cloning: If a single buffer drives too many sinks causing max_fanout or max_cap issues, clone the buffer and split the sinks between the clones.