How to improve timing QOR at CTS and post-CTS?

o   During CTS:

o   Optimize Skew Groups: Define logical skew groups for paths to ensure they are balanced together.

o   Use Non-Default Rules (NDRs): Apply NDRs to critical clock paths to use wider wires and greater spacing, reducing delay and crosstalk susceptibility.

o   Clock Buffer Selection: Ensure the tool is using a good mix of clock buffers and inverters with less variation.

o   Set clock targets appropriately like, skew, latency, DRC.

o   Post-CTS:

o   Run Post-CTS Optimization: Use commands like clock_opt (ICC2) or ccopt_design (Innovus) which are specifically designed to fix timing violations after the clock tree is built.

o   Useful Skew:

o   Clock gate optimization.