o DRC (Design Rule Check): Verifies that the layout geometry adheres to the manufacturing constraints (design rules) specified by the foundry for the target technology node. This includes checks for minimum width, spacing, area, enclosure, overlap, etc., for all layers (metal, poly, diffusion, vias, etc.). Ensures the layout can be physically manufactured with acceptable yield.
o
LVS (Layout Versus Schematic): Compares GDS(Layout)
vs schematic(Netlist). It verifies that the layout correctly implements the
intended logic in netlist. It checks, device types, and device parameters (like
transistor W/L). Checks for shorts, opens, incorrect connections, missing/extra
devices, and parameter mismatches.
o
Antenna Check (Plasma Induced Damage Check):
Verifies compliance with antenna rules, which limit the ratio of connected
metal area (acting as an antenna collecting charge during plasma etching) to
the gate area of connected transistors. Prevents gate oxide damage during
manufacturing.
o
ERC (Electrical Rule Check): Checks for
electrical issues in the layout that might not be caught by LVS or DRC but
could cause functional problems or reliability issues. Examples include:
o
Floating wells or substrates (potential latch-up
risk).
o
Floating gates.
o
Shorted power and ground nets (though often
caught by LVS too).
o
Nets connected only to gate pins without
drivers.
o
Incorrect power/ground connections for specific
cells.
o
Density Checks: Ensures the density of
features (metal, poly, diffusion) across the chip falls within specified
minimum and maximum limits per window size. This is crucial for uniform results
during manufacturing processes like Chemical-Mechanical Polishing (CMP) and etching.
Dummy fill patterns are often added to meet density rules.
o
DFM Checks (Design for Manufacturability: Examples
include redundant via insertion, Dummy Metal fill, recommended rule checks
beyond the mandatory DRCs.
o
PERC: ESD and multiple power domain
related checks.
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