o LVS (Layout Versus Schematic): A critical physical verification process that compares the electrical circuit extracted from the physical layout database (e.g., GDSII, OASIS) against the intended circuit described by the source schematic netlist (e.g., SPICE or Verilog netlist).
o
Inputs:
o Layout
Database: The physical layout design file (GDSII, OASIS)
o Source
Netlist: The "golden" netlist representing the intended circuit
schematic (e.g., SPICE netlist for custom designs, Verilog netlist for digital
designs).
o Rule
Deck: Provided by the foundry, this file tells the LVS tool how to identify
devices (transistors, resistors, capacitors, diodes) from the layout layers,
how to determine connectivity, and how to extract parameters (like W/L for
transistors).
o Configuration/Setup
Files: Files to control the LVS run, specify top cells, map power/ground
names, define device properties to compare, set tolerances, etc.
o Schematic
View vs. Layout View (in LVS context):
§ Schematic
View: Circuit from Golden netlist.
§ Layout
View: Refers to the circuit extracted by the LVS tool from the physical
layout geometry, GDS/OASIS
§ LVS
Comparison: The core LVS process compares the extracted layout netlist
(components, parameters, connectivity) against the source schematic netlist.
o
Is it a Functional Check?
o
No, it doesn’t check functionality of design.
LVS is primarily a structural check.
§ It
verifies that the structure implemented in the layout (which devices
exist, how they are connected, their parameters) matches the intended structure
from the schematic.
§ It
does not verify if the design performs the intended logical function
(e.g., it won't tell you if your adder design actually adds correctly).
Functional verification is done through simulation (RTL, gate-level) or formal
verification (like LEC - Logic Equivalence Checking for digital designs).
§ However,
LVS is crucial for ensuring functionality because errors it catches (like
shorts, opens, wrong connections, wrong device sizes) would almost certainly
cause functional failures.
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