What are the things needed to be taken from sub-blocks to the main block? How do you take logical information of sub-blocks?

o   Logical View (Timing Model - .lib or .db):

o   Provides the timing characteristics of the sub-block's input/output pins (setup/hold times, clock-to-output delays, internal path delays)

o   Defines cell functions (if it's a soft macro with standard cells) or overall block function.

o   Needed for top-level STA and synthesis (if the sub-block is a soft/firm macro).

o   Physical View (Abstract Layout Model - LEF):

o   .lef file of Hard Macro or soft macro/sub blocks.

o   Defines the physical footprint (width, height), pin locations, pin layers, metal blockages (OBS layers) within the sub-block.

o   Constraint View (SDC partial/interface):

o   Interface timing constraints for the sub-block's pins (e.g., specific false paths or multicycle paths internal to the IP that the top level should be aware of, or constraints on its I/O pins).

o   UPF and GDS for merging at last to get complete top-level GDS.