What can cause bad timing at the placement stage?

o   Inaccurate Wire Load Models (WLMs) in Synthesis: Synthesis often uses statistical WLMs to estimate interconnect delay, which can be highly inaccurate compared to the actual delays based on physical placement.

o   Large Distance: Macros or blocks that communicate frequently are placed too far apart, leading to long interconnect delays.

o   Congestion: High placement congestion forces routing detours (even in trial route estimates), increasing wire length and delay.

o   Bad Pin Placement

o   Placement Density: Placing cells too densely, even if not causing severe congestion, results in longer average wire lengths compared to a sparser placement.

o   Critical Path Clustering: The placer might inadvertently place multiple cells from the same critical path far apart while trying to optimize globally or resolve congestion elsewhere.

o   Inadequate Optimization Effort: Tool settings for placement/optimization effort might be too low

o   Constraints Issues: Incorrect or incomplete SDC constraints (e.g., missing exceptions, wrong I/O delays)

o   Physical Effects: Early estimates might start accounting for physical effects like crosstalk (if SI-aware placement is enabled) which were ignored during synthesis.