Why don't we check hold during placement?

o   Ideal Clock Network: During placement (pre-CTS), the PnR tool assumes an "ideal" clock network. This means:

o   Zero Skew: All flip-flops receive the clock edge at the exact same time.

o   Zero Latency (or Ideal Latency): The delay from the clock source to the flip-flops is considered zero or some idealized, non-propagated value.

 

o   Setup time depend on clk period, skew and setup time of FF.

o   Hold Time depends on skew and hold time of FF.

o   Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew => here even if skew is zero, dominating factor is clock period. we have reasonable values in equation to do analysis.

o   Tc2q + Tcomb ≥ Thold + Tskew => skew is dominating factor in equation. here when skew is zero, data path delay just needs to be more than FF hold time. Which in many cases may always be since we don’t have exact skew yet. any hold analysis would be meaningless or highly inaccurate because the dominant factor (skew) is unknown.