o Increased Resistance: Interconnect wires become thinner and taller (to try and mitigate R increase, but R still dominates over C). Via resistance also increases dramatically. This makes the power grid inherently more resistive, leading to higher IR drop (V=I×R).
o
Lower Supply Voltage (Vdd): Operating
voltages are significantly lower (e.g., < 0.8V). This means the allowable
noise margin for IR drop (both static and dynamic) is much smaller (e.g.,
5-10% of Vdd is a smaller absolute voltage). Designs become extremely sensitive
to voltage variations.
o
Higher Current Density: While voltage
decreases, the density of transistors increases significantly, leading to
higher overall current density (J) in the power grid, especially localized
hotspots. Risk of EM.
o
Dynamic IR Drop (Voltage Droop): Faster
switching speeds and higher localized current demands exacerbate dynamic
voltage droop. Providing sufficient instantaneous current through the
high-resistance grid requires a very dense decap cell strategy and a robust
PDN.
o
Complexity of PDN Design: Achieving the
required low resistance and meeting IR/EM targets often necessitates using more
metal layers for the power grid, wider straps, and significantly more vias,
consuming valuable routing resources needed for signals. Balancing power needs
with signal routability becomes harder.
o 7nm
Challenges (includes power/interconnect): https://www.wipro.com/blogs/mohit-bansal/the-benefits-and-challenges-of-7nm-technology/
o Power
Issues at 7nm: https://semiengineering.com/power-issues-causing-more-respins-at-7nm-and-below/
o 7nm
Power Analysis: https://www.design-reuse.com/articles/55324/power-analysis-in-7nm-technology-node.html
0 comments:
Post a Comment