o Voltage islands (or power domains operating at different voltage levels) are created primarily to reduce overall power consumption (both dynamic and static).
o Dynamic
Power Reduction: Pdynamic∝Vdd2. By operating
non-performance-critical blocks (islands) at a lower supply voltage (e.g.,
0.7V) compared to performance-critical blocks (e.g., 0.9V), the dynamic power
consumption of the low-voltage blocks is significantly reduced.
o Static
Power Reduction: Pstatic∝Vdd×Ileakage. Lowering Vdd
directly reduces static power. Additionally, leakage current (Ileakage) itself
often decreases at lower voltages.
o
Requirements for Low Power Design (Techniques
& Special Cells):
o
Power Domains: The design must be
partitioned logically into different power domains based on voltage
requirements or shut-down capability (defined using create_power_domain in
UPF).
o
Voltage Areas: Corresponding physical
regions defined in the floorplan to contain cells belonging to specific power
domains.
o
Isolation Cells: Placed at the boundary
where a signal crosses from a power domain that can be switched off to a
domain that remains ON (or is at a different voltage). Provides steady output
to destination domain when first gates shutoff.
o
Level Shifters: Required when a signal
crosses between two domains operating at different voltage levels (e.g.,
0.7V domain driving a 0.9V domain, or vice-versa).
o
Types: Low-to-High (L->H), High-to-Low
(H->L), Bi-directional.
o
Retention Registers/Flops: Used in power
domains that are switched OFF (power gated) but need to retain their state
(e.g., configuration registers, FSM state registers) so the block can quickly
resume operation upon power-up without full re-initialization.
o
Purpose: Store the flop's value in a
low-leakage "shadow latch" (powered by an always-on supply) just
before the main power is cut, and restore the value when power returns.
o
Control: Require SAVE and RESTORE control
signals, typically from a PMU.
o
Power Switches (Switch Cells): Transistor
networks (usually header - PMOS switches connecting to VDD, or footer - NMOS
switches connecting to VSS, or both) used to physically connect or disconnect
the power supply rails of a switchable power domain from the main power grid.
o
Purpose: Enable power gating (PSO) by
cutting power to idle blocks.
o
Control: Controlled by enable signals
from a PMU. Often implemented as a network or "daisy chain" of switch
cells for robustness.
o
Always-On Cells/Buffering: Logic or nets
that need to remain active even when parts of the design are powered down
(e.g., isolation control signals, retention control)
o Low
Power Implementation Techniques: https://www.ednasia.com/low-power-implementation-techniques-for-asic-physical-design/
o UPF
Special Cells: https://www.techsimplifiedtv.in/2024/07/special-standard-cells-in-upf-ep-3.html
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