What is clock latency? How to reduce latency?

o   Clock Latency (Insertion Delay): The time it takes for the clock signal to propagate from its source (the point where the clock is defined, e.g., a primary input port) to the clock pin of a specific sequential element (sink pin, e.g., a flip-flop's CK pin).

o    Source Latency: Delay from the actual clock origin (e.g., crystal oscillator) to the clock definition point in the design (defined using set_clock_latency -source). This models external delay.

o    Network Latency: Delay from the clock definition point through the clock tree buffers/inverters and interconnect to the sink pin (defined using set_clock_latency or calculated by STA post-CTS).

o   Checking Latency: Use commands like report_ccopt_clock_trees, report_ccopt_skew_groups

o   Reducing Latency:

o    Faster Cells: Use lower-Vt or higher-drive-strength buffers/inverters in the clock tree (trade-off with power).

o    If ICG not placed properly can cause detour and high ID.

o    Strict skew and trans target can add a greater number of buf/inv causing high latency. Targets can be reduced within limit.

o    Use inverters instead of buffers.

§  It doesn’t always help. As we need more number of inverters compared to buffer as buffer can drive longer. Now each inv or buf needs to be connected to net, and lower metal/via has high resistance. Using buffer is better than Frequent use of lower metal for inverters.

o    Use the MaxCap construct to help heavily loaded and therefore slower clock buffers

o    Use NDR and Higher Metal Layers:

o    Balanced Tree Structure:

o   clock buf vs Inv