What is the issue with higher latency?

o   Increased Power Consumption: Longer clock trees generally contain more buffers/inverters and longer nets. This leads to higher power consumption.

o   Increased Area: More buffers/inverters consume more silicon area.

o   CPPR and OCV Impact: longer tree not properly balanced or may not have more common path. Reducing CRPR effect. More cells means more OCV impact and delay variation causing timing closure difficult

o   Increased Jitter Accumulation: Longer paths with more buffers can potentially accumulate more jitter, increasing clock uncertainty and further tightening timing constraints.