o SDC Version: Specifies the SDC standard version used (e.g., set sdc_version 2.1).
o
Units: Defines units for time,
capacitance, resistance, voltage, current, power (e.g., set_units -time ns
...).
o
Clock Definitions:
o
create_clock: Defines primary clocks entering
the design (at ports or internal pins), specifying their source, period,
waveform (duty cycle, edge times).
o
create_generated_clock: Defines clocks generated
internally (e.g., by PLLs, clock dividers/multipliers) based on a master clock.
o
set_clock_groups: Defines relationships between
clocks (synchronous, asynchronous, exclusive).
o
set_clock_latency: Specifies source latency
(external delay to clock definition point) and network latency (estimated or
propagated internal delay).
o
set_clock_uncertainty: Defines margins for clock
skew and jitter.
o
set_clock_transition: Specifies the desired
transition time for clock nets.
o
Input/Output Delays:
o
set_input_delay: Specifies the arrival time of
data at an input port relative to a clock edge. Represents the delay of the
external logic driving the input.
o
set_output_delay: Specifies the required time
for data at an output port relative to a clock edge. Represents the setup time
requirement of the external logic receiving the output.
o
Timing Exceptions:
o
set_false_path: Identifies paths that should be
ignored during timing analysis (logically impossible or irrelevant paths).
o
set_multicycle_path: Specifies paths that are
allowed to take more than one clock cycle to propagate.
o
set_max_delay/set_min_delay: Overrides default
setup/hold checks with specific delay requirements for certain paths.
o
Design Rule Constraints:
o
set_max_transition: Defines the maximum allowed
signal transition time on nets or pins.
o
set_max_capacitance: Defines the maximum allowed
capacitance load on output pins.
o
set_max_fanout: Defines the maximum number of
gates an output pin can drive.
o
External Environment:
o
set_driving_cell: Models the drive strength of
the external logic driving input ports.
o
set_load: Specifies the capacitive load
connected to output ports.
o
Mode-Specific Constraints:
o
set_case_analysis: Sets specific pins/ports to
constant values ('0' or '1') to enable/disable logic for specific modes (e.g.,
functional vs. test).
o
Why Define I/O Delays?
o Constrain Interface Paths: Primary inputs and outputs are startpoints and endpoints for timing paths. Without I/O delays, these paths are unconstrained, and the tool cannot optimize or verify the timing related to external interactions.
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