o DRC (Design Rule Check): checks if the physical layout is as per foundry rules, ensure it can be manufactured reliably with acceptable yield.
o Types
of Rules: Include minimum width, minimum spacing (intra-layer and
inter-layer), minimum area, via enclosure, overlap requirements, antenna rules
(often checked separately but fundamentally DRCs), density rules, and many
complex conditional rules (e.g., end-of-line spacing, notch spacing).
o Fixing
DRCs:
§ Spacing
Violations: Increase the space between the violating shapes (e.g., move
wires further apart).
§ Width/Area
Violations: Increase the width or area of the violating shape.
§ Enclosure/Overlap
Violations: Adjust the size or position of shapes to meet via enclosure or
layer overlap requirements.
§ Manual
Fixing: If handful of DRCs, can be fixed manually within PNR tools.
§ Automated
Fixing: If too many drcs, can use eco_route -fix_drc. Tool can re route and
try to fix drcs.
o
Fixing thousands of DRCs requires a systematic
approach:
§ Categorize
Errors: Use the DRC tool's reporting features to group violations by rule
type and layer.
§ Prioritize:
Focus on systematic errors first which can be implemented by script or
automated way.
§ Scripting:
Write scripts (Tcl, Skill) to automate fixes for repetitive, predictable
violations.
o Tools
Used:
§ Signoff
PV Tools: Industry standards are Siemens Calibre, Cadence Pegasus, Synopsys
IC Validator. These are used for final signoff verification.
§ PnR
Tools: Cadence Innovus and Synopsys ICC2/Fusion Compiler have integrated
DRC engines (often leveraging the signoff engines) for checking and fixing
during place and route.
o DRC
in VLSI: https://www.techsimplifiedtv.in/2023/01/design-rule-check-in-vlsi.html
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