What is a loop violation in DRC fixing?

o   In terms of  STA:

o   When in timing path, there is output of combo logic is used as input in same timing path, it forms, loop causing instability and difficulty in modelling timing for that path.

o   https://www.intel.com/content/www/us/en/docs/programmable/683323/18-1/avoid-combinational-loops.html

o   In terms of DRC: when layer has DPT enabled and layout is forming a loop in such a way that it is not possible to assign mask1/2 to shapes without causing spacing violations.

o   https://semiengineering.com/cut-cut-double-patterning-question/

o   https://semiwiki.com/eda/1962-fixing-double-patterning-errors-at-20nm/#:~:text=Move%20single%20edges%20as%20opposed,which%20make%20the%20design%20uncolorable.