What is IR drop (Static/Dynamic)? Why consider it?

·         For power analysis, each cell's power dissipation has been characterized in the library (.lib) file. For leakage power, the EDA tool simply adds up the leakage power of each cell. (Note: Leakage power is usually state dependent) For dynamic power, the EDA tool either estimates net capacitance before P&R or calculates net capacitance after P&R. The designer has to provide the toggle rate. This can be based on educated guess, experience, simulation, or emulation.

·         IR Drop: it's the reduction in voltage level along the power (VDD) and ground (VSS) distribution network (PDN) due to the resistance (R) of the metal wires/vias and the current (I) flowing through them (Vdrop​=I×R). This means the voltage actually delivered to a standard cell or macro's power pins is lower than the ideal supply voltage at the source (pads/bumps).

·         Static IR Drop: The average voltage drop across the PDN over time, calculated using the average current drawn by the design components (primarily due to leakage current and average switching activity). It uses the total power dissipation to calculate a constant current draw. This current is then multiplied by the equivalent resistance of the power network to arrive at the voltage drop

o    Iavg = leakage current + avg switching current.

o    Avg switching current can be calculated based on vectorless or with given switching activity or vectors.

·         Dynamic IR Drop (Voltage Droop): The transient or peak voltage drop that occurs due to sudden, high peak current demands caused by many cells switching simultaneously (e.g., right after a clock edge). This instantaneous drop can be significantly larger than the static drop and is highly dependent on switching activity patterns and decoupling capacitance effectiveness.

o    No two cells can experience same supply voltage, due to placement, nearby activities thus each std cells have it’s unique dynamic voltage footprint.

o    Cycle to cylcle dynamic voltage variation depends on overall change in peak current, Change in toggle rate of local cells.

·         Why Consider IR Drop?

o    Performance Impact: Reduced voltage at a cell's power pins increases its delay (cells slow down). This can lead to setup violations and limit the maximum operating frequency of the chip.

o    Noise Margin Reduction: Lower supply voltage reduces the noise margin of logic gates, making them more susceptible to functional failures due to crosstalk or other noise sources.

o    Hold Violations: Uneven IR drop across the chip can create local voltage differences that effectively alter clock skew or data path delays in unexpected ways, potentially causing hold violations.

o    Functional Failure: In severe cases, the voltage drop might be large enough that cells fail to operate correctly or sequential elements lose their state (especially critical in low-voltage designs).