Why clock gating timing is difficult to meet?

o   Usually, data path logic is high

o   If gater is not cloned or not cloned efficiently, can create balancing issues and result in timing vios.

o   If latency is not in control or net and high drive strength cells are don’t use can create difficulty in ckg timing closure.

o   Usually, CKG path having negative skew resulting in difficulty in setup fixes. Negative skew because CTS try to balance skews between CKG fanout and FF before it.